Writing data to a memory cell
US9412438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Mar 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.