Memory device
US9412470B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.