Semiconductor package having supporting plate and method of forming the same
US9412720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.