Array substrate and manufacturing method thereof, and display device
US9412760B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 12, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0231
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region sequentially includes a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode; the peripheral circuit region sequentially includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer. An orthogonal projection area of the second circuit line is at least partly overlapped with an orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer. A method for manufacturing the array substrate and a display device including the array substrate are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.