Amplifier dynamic bias adjustment for envelope tracking
US9413298B2 · kind B2 · utility
41Cited by
30References
36Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.