Intelligent packet data register file that prefetches data for future instruction execution
US9417916B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Nov 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each processor has an intelligent packet data register file. One processor is tasked with processing the packet, and its packet data register file caches a subset of the bytes. Some instructions when executed require that the packet data register file supply the execute stage of the processor with certain bytes of the packet data. The register file detects a packet data prefetch trigger condition, and in response determines if it does not store some of the bytes in a prefetch window. If it does not, then it retrieves those bytes from the packet buffer memory, so that it then has all the bytes in the prefetch window. In one example, a subsequently executed instruction uses the prefetched packet data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.