Method and apparatus of a fully-pipelined FFT
US9418047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Oct 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of three bit units (called triplets) are permuted by a shuffler to shuffle the positions of the triplets into different patterns which are used to specific the read/write operation of a memory. For example, the least significant triplet in a conventional counter can be placed in the most significant position of a permuted three triplet pattern. The count of this permuted counter triplet generates addresses that jump 64 positions each clock cycle. These permutations can then be used to generate read and write control information to read from/write to memory banks conducive for efficient Radix-8 Butterfly operation. In addition, one or more triplets can also determine if a barrel shifter or right circular shift is required to shift data from one data lane to a second data lane. The triplets allow efficient FFT operation in a pipelined structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.