Integrated circuit design system and method of generating proposed device array layout
US9418200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.