Security system and methods for integrated devices
US9418247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2013 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/73
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for implementing security mechanisms in integrated devices and related structures. This method can include validating a device ID, generating a random value based on selected seed parameters, performing logic operations from hardware using the random value, and validating the integrated device based on logic operations from software using the random value. The system can include executable instructions for performing the method in a computing system. Various embodiments of the present invention represent several implementations of a security mechanism for integrated devices. These implementations provide several levels of encryption or protection of integrated devices, which can be tailored depending on the hardware and/or software requirements of specific applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.