Synapse array, pulse shaper circuit and neuromorphic system
US9418333B2 · kind B2 · utility
19Cited by
5References
25Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 27, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.