In-memory computational device
US9418719B2 · kind B2 · utility
29Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Nov 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. The computing device additionally includes at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from the first section and a decoder to activate a word line connected to a cell in the column in the second section to write the bit line voltage into the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.