Apparatus for boosting source-line voltage to reduce leakage in resistive memories
US9418761B2 · kind B2 · utility
8Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Dec 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.