Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC
US9418788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Mar 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.