Resistive random access memory structure and method for operating resistive random access memory
US9419053B2 · kind B2 · utility
5Cited by
4References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 21, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random access memory (RRAM) structure including a first transistor, a second transistor and a RRAM cell string is provided. The first transistor and the second transistor are cascaded by electrically connecting a first terminal of the first transistor and the second transistor. The RRAM cell string includes a plurality of memory cells connected with each other and is electrically connected to a second terminal of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.