Non-transparent bridge method and apparatus for configuring high-dimensional PCI-express networks
US9419918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/25
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The descriptions presented herein include explanation of high-dimensional PCI-Express (PCIe) network implementations. The new approaches can facilitate utilization of an efficient protocol (e.g., PCIe, etc.) while enabling implementation of various characteristics and features (e.g., characteristics and features similar to a fat-tree topology, CLOS topology, 2D and 3D topologies, etc.) that would otherwise not be compatible with the protocol. For example, implementation of alternative paths can be enabled and utilized while maintaining compliance with a protocol (e.g., PCIe, etc.) that would otherwise not be compatible with the use of alternative paths. The alternative paths can facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. In one embodiment, presented systems and methods facilitate utilization of a non-transparent bridge circuit configured as an end-point with respect to communications from at least one device while facilitating transmission of the communications on to at least one other device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.