Array substrate, 3D display device and driving method for the same
US9420273B2 · kind B2 · utility
1Cited by
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5Claims
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Key dates
| Filing date | Oct 30, 2013 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jan 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0209
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
According to embodiments of the present invention, the gate lines of the array substrate receive the gate scanning signal in a preset time period. Specifically, the gate lines of pixel units in odd rows are receiving the gate scanning signal in the first time interval of the preset time period, and the gate lines of pixel units in even rows are receiving the gate scanning signal in the second time interval of the preset time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.