Substrate embedding passive element
US9420683B2 · kind B2 · utility
3Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2013 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Apr 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09854
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A substrate embedding a passive element includes a first conductor pattern layer disposed on a lower surface thereof and a second conductor pattern layer disposed on an upper surface thereof; a first via electrically connecting between the passive element and the first conductor pattern layer; and a second via electrically connecting between the passive element and the second conductor pattern layer, in which a volume of the first via is larger than that of the second via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.