Method to enhance programming performance in multilevel NVM devices
US9423961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Mar 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a processor. The interface is configured to communicate with a memory device. The processor is configured to send to the memory device, via the interface, a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device, while inserting in the sequence suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.