SRAM cell layout structure and devices therefrom
US9424385B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Nov 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.