Semiconductor memory device and method for reading the same using a memory cell array including resistive memory cells to perform a single read command
US9424916B2 · kind B2 · utility
1Cited by
16References
12Claims
0Family size
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Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells. Therefore, data of the memory is discriminated by analyzing distribution of the digital code values to monitor a characteristic of a current memory cell array and read the data having reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.