Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

US9425110B1 · kind B1 · utility

Assignee

• NORTHROP GRUMMAN SYSTEMS CORPORATION · US

Inventors

• Jose G. Padilla · South Gate, US
• Philip W. Hon · Hawthorne, US
• Shih-En Shih · Torrance, US
• Roger Tsai · Torrance, US
• Xianglin ZENG · Shanghai, CN

Key dates

• Filing date: Aug 27, 2015
• Grant date: Aug 23, 2016
• Expiry date: Aug 27, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06596
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.