Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material
US9425193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2012 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conducti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.