Syncless unit interval variation tolerant PWM receiver circuit, system and method
US9425781B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K9/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.