Reconfigurable logic gates using chaotic dynamics
US9425799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2015 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/34
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least one chaotic circuit block, a bias voltage generating circuit block, and a threshold circuit block. The encoding circuit block converts a plurality of digital inputs to an analog output. The plurality of digital inputs may comprise at least one data input and at least one control input. At least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to at least one chaotic circuit as the input signal at each iteration. The bias voltage generating circuit block converts a plurality of binary control inputs to a bias voltage. The threshold circuit block compares the output signal with a predetermined threshold, thereby generating a digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.