Redundancy scheme for flash assisted successive approximation register (SAR) analog-to-digital converter (ADC)
US9425814B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described. In one aspect, an ADC is described which uses a Flash-assisted ADC and a Successive Approximation Register (SAR) to provide digital approximations of an input analog voltage to a Capacitor Digital-to-Analog Converter (DAC), which generates a voltage from the digital approximations. The two voltages are compared and the comparison value used as the input for the SAR. After successive approximations, a digital combiner generates the digital conversion value from the outputs of the Flash-assisted ADC and the SAR. In one aspect, the bit cycles required for conversion are reduced by using redundancy and recombination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.