Method for reducing jitter in receivers
US9426004B1 · kind B1 · utility
1Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2015 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | May 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0377
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.