Single-lane, twenty-five gigabit ethernet
US9426096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Aug 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/413
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.