Electrical connection with reduced topography
US9426886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Mar 21, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49124
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.