Voltage regulator stress reducing system
US9430007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jan 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/177
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method for reducing electrical component stress from power cycling is provided. The method may include receiving an indication associated with power cycling an electronic apparatus. The method may also include identifying, based on the received indication, a first one or more groups of electrical components that will not be powered off during the power cycling of the electronic apparatus. The method may further include identifying, based on the received indication, a second one or more groups of electrical components that will be powered off during the power cycling of the electronic apparatus. The method may finally include powering off the second one or more groups of electrical components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.