Scalar optimizations for shaders
US9430199B2 · kind B2 · utility
1Cited by
1References
15Claims
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Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Feb 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45525
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.