Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT
US9430242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2012 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for throttling GPU execution performance to avoid surges in DI/DT. A processor includes one or more execution units coupled to a scheduling unit configured to select instructions for execution by the one or more execution units. The execution units may be connected to one or more decoupling capacitors that store power for the circuits of the execution units. The scheduling unit is configured to throttle the instruction issue rate of the execution units based on a moving average issue rate over a large number of scheduling periods. The number of instructions issued during the current scheduling period is less than or equal to a throttling rate maintained by the scheduling unit that is greater than or equal to a minimum throttling issue rate. The throttling rate is set equal to the moving average plus an offset value at the end of each scheduling period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.