Thread scheduling based on predicted cache occupancies of co-running threads
US9430277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2013 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jul 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.