Cache performance prediction and scheduling on commodity processors with shared caches
US9430287B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Mar 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes assigning a thread performance counter to threads being created in the computing environment, the thread performance counter measuring a number of cache misses for a corresponding thread. The method also includes calculating a self-thread value S as a change in the thread performance counter of a given thread during a predetermined period, calculating an other-thread value O as a sum of changes in all the thread performance counters during the predetermined period minus S, and calculating an estimation adjustment value associated with a first probability that a second set of cache misses for the corresponding thread replace a cache area currently occupied by the corresponding thread. The method also includes estimating a cache occupancy for the thread based on a previous occupancy for the thread, S, O, and the estimation adjustment value, and assigning computing environment resources to the thread based on the estimated cache occupancy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.