Power mode register reduction and power rail bring up enhancement
US9430323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2013 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jul 19, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.