Patent · US Active

Delayed authentication debug policy

US9430347B2 · kind B2 · utility

1Cited by

0References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Michael Neve de Mevergnies · Beaverton, US
Hermann W. Gartler · Portland, US
Michael S. Bair · Banks, US

Key dates

Filing date	Dec 23, 2014
Grant date	Aug 30, 2016
Priority date	—
Expiry date	Mar 3, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/27
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.