Managing high speed memory
US9430365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for managing a high speed memory. An index entry indicates a storage unit in the high speed memory. A corresponding non-free index is set for a different type of low speed memory. The indicated storage unit in the high speed memory is assigned to a corresponding low speed memory by including the index entry in the non-free index. The storage unit in the high speed memory is recovered by demoting the index entry from the non-free index. The mechanism acquires a margin performance loss corresponding to a respective non-free index in response to receipt of a demotion request. The margin performance loss represents a change in a processor read operation time caused by performing a demotion operation in a corresponding non-free index. The mechanism compares the margin performance losses of the respective non-free indexes and selecting a non-free index whose margin performance loss satisfies a demotion condition as a demotion index. The mechanism selects an index entry from the demotion index to perform the demotion operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.