Chip packaging structures and treatment methods thereof
US9431215B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Apr 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.