Stacked damascene structures for microelectronic devices
US9431343B1 · kind B1 · utility
1Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Apr 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/58
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect structure. The dual-damascene interconnect structure and the single-damascene line structure may each include multiple line segments that are arranged in a brick wall pattern. The brick wall pattern may also be used with two or more single-damascene line structures. Various microelectronic devices and related fabrication methods are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.