Substrate for mounting multiple power transistors thereon and power semiconductor module
US9431376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Nov 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.