Vertical memory devices and methods of manufacturing the same
US9431418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Apr 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.