Semiconductor memory device and method for manufacturing same
US9431419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
Abstract
According to one embodiment, a first layer; a stacked body provided above the first layer and including a plurality of electrode layers separately stacked each other; a second layer provided between the first layer and the stacked body; an intermediate layer provided between the first layer and the second layer; a semiconductor body provided in the stacked body, the second layer, the intermediate layer and the first layer, the semiconductor body extending in a stacking direction of the stacked body; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The semiconductor body includes a side surface connected with the intermediate layer in the vicinity of a boundary between the first layer and the second layer. At least one of the first layer and the second layer has conductivity and is connected with the intermediate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.