Array substrate and manufacturing method thereof
US9431436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2010 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Aug 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing an array substrate is disclosed. A first conductive pattern, a first insulating layer, a second conductive pattern, and a second insulating layer on a base substrate is successively formed. The second insulating layer and the first insulating layer are patterned with a double-tone mask. At least a half lap joint via hole in the second insulating layer, and at least a full lap joint via hole in both the first insulating layer and the second insulating layer is formed. The second conductive pattern corresponds to a part of the half lap joint via hole, and the first conductive pattern corresponds to the whole of the full lap joint via hole. A third conductivity pattern is formed on the surface of the second conductivity pattern and the first insulating layer and a fourth conductive pattern is formed on the surface of the first conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.