Display panel and method of manufacturing the same
US9431437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0231
Abstract
A display panel includes a gate electrode and a gate line on a substrate, a gate insulating layer and an active layer sequentially on the gate electrode and the gate line, a planarization layer which is on the substrate and compensates for a step difference between the substrate, and the gate electrode and the gate line, respectively, source and drain electrodes on the active layer overlapping the gate electrode and spaced apart from each other, a data line on the active layer and crossing the gate line, a protective layer which covers the planarization layer, the source and drain electrodes, and the data line, a contact hole defined in the planarization layer and partially exposing the drain electrode, and a pixel electrode on the protective layer and electrically connected to the drain electrode through the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.