Methods and systems of impedance source semiconductor device protection
US9431819B2 · kind B2 · utility
2Cited by
16References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jan 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/005
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrical network configured to suppress voltage transients is disclosed. The network includes a capacitor and an electrical impedance in parallel with a diode. The capacitor is in series with the parallel connected diode and electrical impedance, and the electrical network is configured to suppress voltage transients occurring across the series combination of the capacitor and the parallel connected diode and electrical impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.