Multi-bit standard cells for consolidating transistors with selective sourcing
US9432003B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jun 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same sourcing. A third set of transistors can then be created. This third set has fewer transistors than the second set. The second set of transistors can be deleted in the standard cell. The third set of transistors can be connected to the circuits of the standard cell. This method can significantly extend circuit consolidation to improve the area benefit of multi-bit standard cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.