Variable delay element
US9432008B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 22, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jul 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.