Clock data recovery circuit and a method of operating the same
US9432028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.