PLL-VCO based integrated circuit aging monitor
US9432031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.