Mismatch correction of attenuation capacitor in a successive approximation register analog to digital converter
US9432044B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Dec 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality of most significant bit (MSB) capacitors in a first segment using a calibration DAC. The first segment is connected to the second segment by an attenuation capacitor. Each of the error voltages corresponding to the MSB capacitors is digitized to form a set of digitized error voltages. An error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the second segment is calculated by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor is mitigated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.