Method and system for a programmable parallel computation and data manipulation accelerator
US9432180B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Methods and systems are provided for a programmable parallel computation and data manipulation accelerator that may be used, for example, in cryptographic calculations. They allow acceleration of a broad variety of cryptographic algorithms and/or portions of algorithms, and are not algorithm specific. This system comprises a butterfly and inverse butterfly multiplexing permuter network and a lookup table. This system may allow replication of input registers, “expansion,” so that an individual bit may be used in multiple calculations in parallel, accelerating completion of the cryptographic algorithm. The system may allow “diffusion” of the expanded bits through the system's butterfly and inverse butterfly network, and may provide for “confusion” of the resulting bits through the system's lookup table. In some implementations, the system may allow completion of a computation within an algorithm within one clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.